基于矩阵表示的CMOL电路容错映射
PDF下载 (380)徐鹏飞,夏银水,查晓婧,顾贤贵.基于矩阵表示的CMOL电路容错映射[J].宁波大学学报(理工版),2021,34(2):1-8.DOI:
XU Pengfei,XIA Yinshui,ZHA Xiaojing,GU Xiangui.Defect-tolerant mapping of CMOL circuit expressed by matrix[J].Journal of Ningbo University(Natural Science & Engineering Edition),2021,34(2):1-8.DOI:
| Title: | Defect-tolerant mapping of CMOL circuit expressed by matrix |
| 作者: | 徐鹏飞, 夏银水, 查晓婧, 顾贤贵 |
| Author(s): | XU Pengfei, XIA Yinshui, ZHA Xiaojing, GU Xiangui |
| 关键词: | 单元容错映射; 矩阵表示; memetic算法 |
| Keywords: | CMOL; defect-tolerant cell mapping; matrix representation; memetic algorithm |
| 分类号: | TP311 |
| 文献标识码: | A |
| 摘要: | 针对存在缺陷的CMOS/纳米分子混合(CMOS/nanowire/MOLeclular hybrid, CMOL)电路的单元容错映射问题, 提出一种基于矩阵表示的CMOL电路容错映射方法. 首先, 将逻辑电路和CMOL电路建模为矩阵表示; 然后采用文化基因(memetic)算法进行矩阵间可匹配字符的搜索, 采用小矩阵元值优先匹配的策略完成单元缺陷容忍映射. ISCAS测试电路的实验结果表明, 与已有方法相比, 本文方法在求解速度上有36.98%的提升. |
| Abstract: | To address the problem of cell defect-tolerant mapping in flawed CMOS/nanowire/molecular hybrid (CMOL) circuits, a matrix-based defect-tolerant mapping method for CMOL circuits is proposed. The logic circuit and CMOL circuit are first expressed by a matrix respectively, followed by using the memetic algorithm to search for matching characters between the matrices. The matching strategy with priority assigned to small matrix element value is used to complete the cell defect-tolerance mapping. The experimental results of the ISCAS benchmarks show that, compared with the existing approaches, the CPU runtime of the proposed method is increased by 36.98%. |
| 参考文献 /References: | [1] Likharev K K, Strukov D B. CMOL: Devices, Circuits and Architectures[M]//Cuniberti G, Richter K, Fagas G. Introducing Molecular Electronics. Heidelberg: Springer, 2005, 680:447-477. [2] Lu W, Lieber C M. Nanoelectronics from the bottom up [J]. Nature Materials, 2007, 6(11):841-850. [3] Likharev K. Electronics Below 10 nm[M]//Greer J, Korkin A, Labanowski J. Nano and Giga Challenges in Microelectronics. Amsterdam: Elsevier, 2003:27-68. [4] Xia Y S, Chu Z F, Hung W N N, et al. An integrated optimization approach for nanohybrid circuit cell mapping[J]. IEEE Transactions on Nanotechnology, 2011, 10(6):1275-1284. [5] Sait S M, Arafeh A M. Efficient CMOL nanoscale hybrid circuit cell assignment using simulated evolution heuristic [C]//Proceedings of the Great Lakes Symposium on VLSI, New York: ACM Press, 2012:21-26. [6] Sait S M, Oughali F C, Arafeh A M. Engineering a memetic algorithm from discrete Cuckoo search and Tabu search for cell assignment of hybrid nanoscale CMOL circuits[J]. Journal of Circuits, Systems and Computers, 2016, 25(4):1650023. [7] Sait S M, Arafeh A M. Cell assignment in hybrid CMOS/nanodevices architecture using Tabu search[J]. Applied Intelligence, 2014, 40(1):1-12. [8] Farazmand N, Tahoori M B. Multiple fault diagnosis in crossbar nano-architectures[C]//2010 15th IEEE European Test Symposium, IEEE Computer Society, 2010:94-99. [9] Strukov D B, Likharev K K. CMOL FPGA: A reconfigurable architecture for hybrid digital circuits with two-terminal nanodevices[J]. Nanotechnology, 2005, 16 (6):888-900. [10] Hung W N N, Gao C J, Song X Y, et al. Defect-tolerant CMOL cell assignment via satisfiability[J]. IEEE Sensors Journal, 2008, 8(6):823-830. [11] 陈定亨, 夏银水, 储著飞. 缺陷无意识的CMOL单元容错映射[J]. 计算机辅助设计与图形学学报, 2017, 29(11):2133-2139. [12] Sait S M, Arafeh A M. Reconfiguration-based defect- tolerant design automation for hybrid CMOS/nanofabrics circuits using evolutionary and non-deterministic heuristics [J]. Arabian Journal for Science and Engineering, 2015, 40(9):2515-2529. [13] Chen D, Xia Y, Wang Z. Stuck-at-close defect propagation and its blocking technique in CMOL cell mapping[J]. Microelectronics Journal, 2018, 72(2):100- 108. [14] 查晓 , 夏银水, 储著飞. 动态分层及其在CMOL电路缺陷容忍映射优化中的应用[J]. 计算机辅助设计与图形学学报, 2019, 31(8):1457-1466. [15] 陈定亨. CMOL电路的容错映射研究[D]. 宁波: 宁波大学, 2018. [16] Chu Z F, Xia Y S, Hung W N N, et al. A memetic approach for nanoscale hybrid circuit cell mapping[C]// 2010 13th Euromicro Conference on Digital System Design, IEEE Computer Society, 2010. [17] G?ren S, Ugurdag H F, Palaz O. Defect-aware nanocrossbar logic mapping through matrix canonization using two-dimensional radix sort[J]. ACM Journal on Emerging Technologies in Computing Systems, 2011, 7(3):1-16. [18] Brglez F, Bryan D, Kozminski K. Combinational profiles of sequential benchmark circuits[C]//Proceedings of IEEE International Symposium on Circuits and Systems, IEEE Computer Society, 1989:1929-1934. |
| 备注/Memo: | 收稿日期: 2020-08-10. 宁波大学学报(理工版)网址: http://journallg.nbu.edu.cn/ 基金项目: 国家自然科学基金(61571248). 第一作者: 徐鹏飞(1995-), 男, 湖北钟祥人, 在读硕士研究生, 主要研究方向: 逻辑综合与优化. E-mail: 1079290675@qq.com *通信作者: 夏银水(1963-), 男, 浙江余姚人, 研究员, 主要研究方向: 集成电路逻辑综合与优化. E-mail: xiayinshui@nbu.edu.cn 宁波大学学报(理工版)网址:http://journallg.nbu.edu.cn/ |