基于沟长偏置的近阈值逻辑漏功耗减小技术
PDF下载 (405)范晓慧,邬杨波,倪海燕.基于沟长偏置的近阈值逻辑漏功耗减小技术[J].宁波大学学报(理工版),2013,26(03):45-50.DOI:
FAN Xiao-hui,WU Yang-bo,NI Hai-yan.Gate-length Biasing for Near-threshold Logic Leakage Reduction[J].Journal of Ningbo University(Natural Science & Engineering Edition),2013,26(03):45-50.DOI:
| Title: | Gate-length Biasing for Near-threshold Logic Leakage Reduction |
| 作者: | 范晓慧, 邬杨波, 倪海燕 |
| Author(s): | FAN Xiao-hui, WU Yang-bo, NI Hai-yan |
| 关键词: | 亚阈值漏电流; 沟长偏置; 近阈值逻辑; 漏功耗减小 |
| Keywords: | sub-threshold leakage; gate-length biasing; near-threshold logic; leakage power reduction |
| 分类号: | TN402 |
| 文献标识码: | A |
| 摘要: | 随着集成电路芯片特征尺寸的不断缩小, 减小漏功耗已成为集成电路设计技术的焦点之一. 在近阈值逻辑电路中, 亚阈值漏电流是其最主要漏电流的构成. 根据MOS器件沟道长度与亚阈值漏电流之间的非线性关系, 通过适度提高MOS器件的沟道长度从而降低CMOS逻辑电路的漏功耗, 形成了基于沟长偏置的漏功耗减小技术. 应用HSPICE软件对基于45nm PTM工艺参数沟长偏置为8%的基本逻辑门电路、镜像加法器和传输门加法器的漏电流进行了仿真测试, 实验结果表明漏电流约下降了39%~44%. 因此沟长偏置技术是一种有效的适用于近阈值逻辑的漏功耗减小技术. |
| Abstract: | With processing chips scaling down, leakage power reduction has become one of the most important design concerns. In this paper, we propose small biases of transistor gate-length to further minimize leakage power based on the fact that the sub-threshold leakage current is the main component of the total leakage in near-threshold logic circuits. Due to the super-linearity between sub-threshold current and gate length, the leakage current reduction can be considerably achieved by slightly increasing the gate-length. Three basic logic gates, a mirror adder and a transmit adder with 8% gate-length biasing are realized and simulated using HSPICE at a 45nm CMOS process with the PTM model. Simulation results show that the leakage current of those circuits is reduced 39%-44% compared with the nominal gate-length ones. Therefore, the gate-length biasing technique is an attractive approach for low leakage near-threshold circuits. |
| 参考文献 /References: | [1] Paul B C, Agarwal A, Roy K. Low-power design techniques for scaled technologies Integration[J]. The VLSI Journal, 2006, 39(2):64-89. [2] Gupta K, Raychowdhury A, Roy K. Digital computation in subthreshold region for ultralow-power operation: A device-circuit-architecture codesign perspective[J]. Pro- ceedings of the IEEE, 2010, 98(2):160-190. [3] Borkar S. Getting gigascale chips: Challenges and opportunities in continuing moore’s law[J]. ACM Queue, 2003, 1(7):28-33. [4] Wang A, Calhoun B H, Chandrakasan A P. Sub-threshold design for ultra low-power systems[M]. New York: Springer, 2006:12-102. [5] Bellaouar A, Elmasry M I. Low-power digital VLSI design circuits and systems[M]. Boston: Kluwer Academic Press, 1995. [6] Chang J, Pedram M. Energy minimization using multiple supply voltages[J]. IEEE Trans VLSI Syst, 1997, 5(4): 436-443. [7] Kim S, Papaefthymiou M C. Ture single-phase adiabatic circuitry[J]. Very Large Scale Integration (VLSI) Systems, 2001, 9(1):52-63. [8] Hu Jiangping, Xu Tiefeng, Li Hong. A Lower-power register file based on complementary pass-transistor adiabatic logic[J]. IEICE Trans on Information and Systems, 2005, 88(7):1479-1485. [9] Dreslinski R G, Wieckowski M, Blaauw D, et al. Near-threshold computing: Reclaiming Moore’s law through energy efficient integrated circuits[J]. Pro- ceedings of the IEEE, 2010, 98(2):253-266. [10] Markovic D, Wang C C, Alarcon L P, et al. Ultralow- power design in near-threshold region[J]. Proceedings of the IEEE, 2010, 98(2):237-252. [11] Wu Yangbo, Hu Jiangping. Low-voltage MOS current mode logic for low-power and high speed applications[J]. Information Technology Journal, 2011, 10(12):2470- 2475. [12] Kim K K, Kim Y B, Choi M, et al. Leakage minimization technique for nanoscale CMOS VLSI[J]. IEEE Design and Test of Computers, 2007, 24(4):322-330. [13] Fallah F, Pedram M. Standby and active leakage current control and minimization in CMOS VLSI circuits[J]. IEICE Trans on Electronics, 2005, E88-C(4):509-519. [14] Gupta P, Kahng A B, Sharma P, et al. Gate-length biasing for runtime-leakage control[J]. IEEE Trans on Computer- Aided-Design of Intergrated Circuits and Systems, 2006, 25(8):1475-1485. [15] Kim J, Oh C, Shin Y. Minimizing leakage power of sequential circuits through mixed-Vt flip-flops and multi-Vt combinational gates[J]. ACM Transactions on Design Automation of Electronic Systems, 2009, 15(1): 14-22. [16] Narendra S G, Chandrakasan A. Leakage in nanometer CMOS technologies[M]. New York: Springer, 2006. [17] Xi X, Dunga M, He J, et al. BSIM4.6.4 MOSFET model user’s manual[EB/OL]. [2009-12-12]. http://www-device. eecs.berkeley. edu/~bsim3/bsim4.html. |
| 备注/Memo: | 收稿日期: 2012?11?14. 基金项目: 国家自然科学基金（61071049）; 宁波市自然科学基金（2011A610102）; 浙江省教育厅科研项目（Y201120962）.第一作者: 范晓慧（1988－）, 女, 河南郑州人, 在读硕士研究生, 主要研究方向: 低功耗集成电路设计. E-mail: easyfanxh@126.com *通信作者: 邬杨波（1972－）, 男, 浙江奉化人, 副教授, 主要研究方向: 集成电路设计. E-mail: wuyangbo@nbu.edu.cn 宁波大学学报（理工版）网址：http://journallg.nbu.edu.cn/ |
