基于逻辑复合门映射的电路面积优化
PDF下载 (342)岑旭梦,王伦耀 *,夏银水.基于逻辑复合门映射的电路面积优化[J].宁波大学学报(理工版),2016,29(4):38-43.DOI:
CEN Xu-meng,WANG Lun-yao *,XIA Ying-shui.Area Optimization Based on the Complex Logic Gates Mapping[J].Journal of Ningbo University(Natural Science & Engineering Edition),2016,29(4):38-43.DOI:
| Title: | Area Optimization Based on the Complex Logic Gates Mapping |
| 作者: | 岑旭梦, 王伦耀 *, 夏银水 |
| Author(s): | CEN Xu-meng, WANG Lun-yao *, XIA Ying-shui |
| 关键词: | 复合门; 映射; 逻辑优化 |
| Keywords: | BDD; complex gate; mapping; logic optimization |
| 分类号: | TN47; TP391 |
| 文献标识码: | A |
| 摘要: | 提出了一种基于复合门映射的电路面积优化方法. 该方法首先通过BDD结构的拆分将待优化的逻辑电路转化为由二输入基本逻辑门组成的多级逻辑网络, 然后利用复合门搜索和等效转换算法将逻辑网络中适合复合门实现的子结构用相应的复合门替换. 提出的优化算法用C语言编程实现, 并用MCNC电路进行了测试. 测试结果表明, 相比于ABC和BDS软件结果, 经算法优化后, 电路的节点数可分别减少约37%和29%. |
| Abstract: | In this paper, an area optimization method is proposed based on the complex gates mapping. In order to map the complex gates, a logic circuit is turned into a multi-level network which consists of 2-input basic logic gates using the BDD decomposition. Then algorithms are designed to include searching for the sub-networks that can be replaced by the suitable complex gates, and the equivalent conversion between two different complex gates is utilized. The proposed method is implemented in C and tested by MCNC benchmarks. The experimental results show that, compared to the ABC and BDS tools, the number of the nodes of the tested circuits can be reduced by about 35% and 29% respectively by applying the proposed method. |
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| 备注/Memo: | 收稿日期: 2015－11－16. 宁波大学学报（理工版）网址: http://journallg.nbu.edu.cn/ 基金项目: 国家自然科学基金（61131001, 61471211）. 第一作者: 岑旭梦（1992－）, 男, 浙江宁波人, 在读硕士研究生, 主要研究方向: 数字集成电路逻辑综合和优化. E-mail: cenxumeng@qq.com *通信作者: 王伦耀（1972－）, 男, 浙江宁波人, 教授, 主要研究方向: 数字集成电路逻辑综合和优化. E-mail: wanglunyao@nbu.edu.cn 宁波大学学报（理工版）网址：http://journallg.nbu.edu.cn/ |
