基于AIG的多级逻辑电路延迟近似优化
PDF下载 (271)赵维凯,于宗源,王伦耀.基于AIG的多级逻辑电路延迟近似优化[J].宁波大学学报(理工版),2023,36(1):35-41.DOI:
ZHAO Weikai,YU Zongyuan,WANG Lunyao.AIG based delay optimization of multilevel logic circuits using approximate computing technique[J].Journal of Ningbo University(Natural Science & Engineering Edition),2023,36(1):35-41.DOI:
| Title: | AIG based delay optimization of multilevel logic circuits using approximate computing technique |
| 作者: | 赵维凯, 于宗源, 王伦耀 |
| Author(s): | ZHAO Weikai, YU Zongyuan, WANG Lunyao |
| 关键词: | 近似计算; 逻辑优化; 误差约束; 多级电路; 延迟优化 |
| Keywords: | approximate calculation; logic optimization; error constraint; multi-level circuit; delay optimization |
| 分类号: | TN431.2 |
| 文献标识码: | A |
| 摘要: | 在对多级逻辑电路延迟进行优化中, 提出了一种针对关键路径中节点输出的近似替换方法, 用于实现延迟优化. 提出的算法先建立待优化电路的关键路径集合, 然后通过选取每一条关键路径中错误率影响最小的节点构成待优化节点集, 再结合提出的节点输出近似替换技术, 在错误率约束下实现节点删除和关键路径压缩, 进而达到多级逻辑电路延迟优化. 提出的算法用C++和ABC工具内置命令编程实现, 使用ISCAS85以及LGSynth91电路进行测试. 实验结果显示, 与已提出的常量替换方法相比, 面积和延迟优化效果分别提升22.96%和31.49%. 同时相较于最新提出的针对延迟优化的算法, 在延迟优化效果相近的情况下, 算法运行时间上有61.88%的提升. |
| Abstract: | In order to optimize the delay of multi-level circuits, an algorithm using the approximate replacement of the output node in critical path is proposed for delay optimization purposes. In the algorithm, those critical paths which can be optimized are searched first. Then, the nodes in each critical path with the lowest error rate are selected to form an approximate replacement node set. Finally, by deleting those nodes using approximate replacement under the constraint of error rate, the critical paths are shortened, and the delay is improved. The proposed algorithm is programmed with C++, built-in commands in ABC tools and tested with ISCAS85 and LGSynth91 benchmarks. The experimental results show that compared with the proposed constant replacement methods, the area and delay are improved by 22.96% and 31.49% respectively. Meanwhile, compared with the newly proposed algorithm, our algorithm running timing is improved by 61.88% while the optimization of delay and area remains similar. |
| 参考文献 /References: | [1] Xu Q, Mytkowicz T, Kim N S. Approximate Computing: A Survey[J]. IEEE Design & Test, 2016, 33(1):8-22. [2] Liu W, Lombardi F, Shulte M. A retrospective and prospective view of approximate computing[J]. Proceedings of the IEEE, 2020, 108(3):394-399. [3] Jiang H, Liu C, Liu L, et al. A review, classification, and comparative evaluation of approximate arithmetic circuits [J]. ACM Journal on Emerging Technologies in Computing Systems, 2017, 13(4):1-34. [4] Scarabottolo I, Ansaloni G, Constantinides G A, et al. Approximate logic synthesis: A survey[J]. Proceedings of the IEEE, 2020, 108(12):2195-2213. [5] Venkataramani S, Roy K, Raghunathan A. Substitute-and- simplify: A unified design paradigm for approximate and quality configurable circuits[C]//Design, Automation & Test in Europe Conference & Exhibition (DATE), Grenoble, France, 2013:1367-1372. [6] Su S, Meng C, Yang F, et al. VECBEE: A versatile efficiency-accuracy configurable batch error estimation method for greedy approximate logic synthesis[J/OL]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems [2022-01-09]. http://doi.org/10.1109/TCAD.2022.3149717. [7] Pasandi G, Peterson M, Herrera M, et al. Deep-PowerX: A deep learning-based framework for low-power approximate logic synthesis[C]//Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design, 2020:73-78. [8] Meng C, Qian W, Mishchenko A. ALSRAC: Approximate logic synthesis by resubstitution with approximate care set[C]//2020 57th ACM/IEEE Design Automation Conference, San Francisco, 2020:1-6. [9] Chandrasekharan A, Soeken M, Gro?e D, et al. Approximation-aware rewriting of AIGs for error tolerant applications[C]//2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2016:1-8. [10] Zhou Z, Yao Y, Huang S, et al. DALS: Delay-driven approximate logic synthesis[C]//2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2018:1-7. [11] Wang Y, Wenger S, Wen J, et al. Review of error resilient coding techniques for real-time video communications[J]. IEEE Signal Processing Magazine, 2000, 17(4):61-82. [12] Scarabottolo I, Ansaloni G, Constantinides G A, et al. A formal framework for maximum error estimation in approximate logic synthesis[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2022, 41(4):840-853. [13] Mishchenko A, Chatterjee S, Brayton R. DAG-aware AIG rewriting: A fresh look at combinational logic synthesis[C]//2006 43rd ACM/IEEE Design Automation Conference, San Francisco, 2006:532-535. [14] Brayton R, Mishchenko A. ABC: An academic industrial-strength verification tool[M]//Computer Aided Verification. Berlin, Heidelberg: Springer Berlin Heidelberg, 2010:24-40. [15] Brand D. Verification of large synthesized designs[C]//Proceedings of 1993 International Conference on Computer Aided Design (ICCAD), Santa Clara, CA, 1993: 534-537. [16] Mishchenkoet A. ABC: System for Sequential Logic Synthesis and Formal Verification[DB/OL]. [2021-12-15]. https://github.com/berkeley-abc/abc. [17] Yang S. Logic synthesis and optimization benchmarks user guide version 3.0[EB/OL]. [2022-01-09]. https://max.book118.com/html/2017/0724/123971096.shtm. |
| 备注/Memo: | 收稿日期: 2022-03-22. 宁波大学学报(理工版)网址: http://journallg.nbu.edu.cn/基金项目: 国家自然科学基金(62131010, 61471211, 61871242).第一作者: 赵维凯(1997-), 男, 浙江温州人, 在读硕士研究生, 主要研究方向: 集成电路综合和优化. E-mail: 745112451@qq.com*通信作者: 王伦耀(1972-), 男, 浙江宁波人, 教授, 主要研究方向: 集成电路综合和优化. E-mail: wanglunyao@nbu.edu.cn 宁波大学学报(理工版)网址:http://journallg.nbu.edu.cn/ |