基于虚拟单元映射的电路面积优化算法
PDF下载 (522)罗文强,王伦耀 *,岑旭梦,夏银水.基于虚拟单元映射的电路面积优化算法[J].宁波大学学报(理工版),2018,31(1):52-58.DOI:
LUO Wen-qiang,WANG Lun-yao *,CEN Xu-meng,XIA Yin-shui.Area optimization using virtual cells mapping[J].Journal of Ningbo University(Natural Science & Engineering Edition),2018,31(1):52-58.DOI:
| Title: | Area optimization using virtual cells mapping |
| 作者: | 罗文强, 王伦耀 *, 岑旭梦, 夏银水 |
| Author(s): | LUO Wen-qiang, WANG Lun-yao *, CEN Xu-meng, XIA Yin-shui |
| 关键词: | 逻辑优化; 映射算法; 逻辑努力 |
| Keywords: | library-free; logical optimization; mapping algorithms; logical effort |
| 分类号: | TP391.41 |
| 文献标识码: | A |
| 摘要: | 相比较于标准单元库映射, library-free映射中采用的动态生成的虚拟单元, 具有更大的灵活性, 因而在电路面积优化上往往可以取得更好的效果. 本文提出的基于虚拟单元的面积优化算法包括面积估算和覆盖策略两部分. 在面积估算上提出了基于n元树和逻辑努力的虚拟单元的CMOS电路实现及面积估算方法. 在覆盖策略上提出了一种带有局部寻优策略的离散粒子群优化算法. MCNC测试电路的实验结果表明, 相比较于标准单元库映射, 对于绝大多数电路, 本文给出的算法可以使电路面积得到进一步的优化. |
| Abstract: | Compared to the standard cells mapping, the cell in library-free mapping is virtual, and generated dynamically. The flexibility of virtual cell offers a way for area optimization in the course of mapping. The area optimization in this paper includes two parts: area estimation and covering algorithm. The area estimation consists of the n-ary tree based virtual cell generation and the logic effort based cell area estimation. In covering algorithm, a discrete particle swarm optimization algorithm with local search strategy is presented for global area optimization. The proposed area optimization algorithm is tested under MCNC (Microelectronics Center of North Carolina) benchmarks. The experimental results suggest that compared with the standard cells mapping, for the most of circuits, the proposed algorithm can further optimize the circuit area. |
| 参考文献 /References: | [1] 岑旭梦, 王伦耀, 夏银水. 基于逻辑复合门映射的电路面积优化[J]. 宁波大学学报(理工版), 2016, 29(4):38-43. [2] El-Masry H, Al-Khalili D. Cell stack length using an enhanced logical effort model for a library-free paradigm [EB/OL]. [2016-04-05]. http://ieeexplore.ieee.org/document/6122371/. [3] Possani V N, Callegaro V, Reis A I, et al. Graph-based transistor network generation method for supergate design[J]. IEEE transactions on very large scale integration (VLSI) systems, 2016, 24(2):692-705. [4] Conceicao C, Posser G, Reis R. Reducing the number of transistors with gate clustering[EB/OL]. [2016-12-28]. http://ieeexplore.ieee.org/document/7451035/. [5] Reis A I. Covering strategies for library free technology mapping[EB/OL]. [2015-09-16]. http://ieeexplore.ieee.org/document/803115/. [6] Marques F S, Rosa Jr L S, Ribas R P, et al. DAG based library-free technology mapping[EB/OL]. [2016-08-21]. https://dl.acm.org/citation.cfm?doid=1228784.1228857. [7] Pullerits M, Kabbani A. Area minimization for library-free synthesis[EB/OL]. [2016-02-07]. http://ieeexplore.ieee.org/document/5393800/. [8] Sutherland I, Sproull B, Harris D. Logical effort: designing fast CMOS circuits[M]. Burlington: Morgan Kaufmann Publishers Inc., 1999. [9] 郭文忠, 陈国龙, 彭少君, 等. 求解VLSI电路划分问题的混合粒子群优化算法[J]. 软件学报, 2011, 22(5):833-842. [10] 刘红, 曹颖, 隆腾舞. 基于改进离散粒子群优化算法的容差电路故障特征提取[J]. 兵工学报, 2015, 36(8):1494-1501. [11] Vemuri N, Kalla P, Tessier R. BDD-based logic synthesis for LUT-based FPGAs[J]. Acm Transactions on Design Automation of Electronic Systems, 2002, 7(4): 501-525. [12] Jain A, Bryant R E. Inverter minimization in multi- level logic networks[EB/OL]. [2015-10-19]. http://ieeexplore.ieee.org/document/580098/. [13] Berkeley Logic Synthesis and Verification Group. ABC: system for sequential logic synthesis and formal verification[EB/OL]. [2016-10-08]. https://bitbucket.org/alanmi/abc. |
| 备注/Memo: | 收稿日期: 2017－05－18. 宁波大学学报（理工版）网址: http://journallg.nbu.edu.cn/基金项目: 国家自然科学基金（61471211, 61571248, 61501268）.第一作者: 罗文强（1991－）, 男, 福建浦城人, 在读硕士研究生, 主要研究方向: 逻辑综合与优化. E-mail: iroche@126.com*通信作者: 王伦耀（1972－）, 男, 浙江宁波人, 教授, 主要研究方向: 逻辑综合与优化. E-mail: wanglunyao@nbu.edu.cn 宁波大学学报（理工版）网址：http://journallg.nbu.edu.cn/ |
