基于对抗网络的可配置加解密硬件优化设计
PDF下载 (452)涂江涛,张会红,张跃军*.基于对抗网络的可配置加解密硬件优化设计[J].宁波大学学报(理工版),2026,39(1):1-7.DOI:10.20098/j.cnki.1001-5132.2025.0711
TU Jiangtao,ZHANG Huihong,ZHANG Yuejun.Configurable encryption and decryption hardware design based on adversarial networks[J].Journal of Ningbo University(Natural Science & Engineering Edition),2026,39(1):1-7.DOI:10.20098/j.cnki.1001-5132.2025.0711
| Title: | Configurable encryption and decryption hardware design based on adversarial networks |
| 作者: | 涂江涛, 张会红, 张跃军* |
| Author(s): | TU Jiangtao, ZHANG Huihong, ZHANG Yuejun |
| 关键词: | 神经密码学; 对抗神经网络; 可配置; 电路优化设计 |
| Keywords: | neural cryptography; adversarial neural networks; configurable; optimized circuit design |
| 分类号: | TP391 |
| DOI: | 10.20098/j.cnki.1001-5132.2025.0711 |
| 文献标识码: | A |
| 摘要: | 随着神经密码学的出现，越来越多研究使用神经网络来训练加解密算法，其中采用对抗网络可实现端到端的高安全加解密，但存在开销大、速度慢等问题。通过对运算单元核心、数据存储架构和数据流行为进行协同优化设计，提出一种面向神经网络的可配置加解密硬件设计方案。该方案首先对加解密模型进行硬件友好型优化，完成网络训练和量化；然后，采用Winograd+DSP48的卷积加速方法，将所需96个乘法器降低到32个；最后，设计CPU控制与调度系统架构，结合动态控制加速器的操作模式，实现高性能可配置加解密硬件电路。实验结果表明，所提方案最高工作频率为133 MHz，功耗为32.4 mW，吞吐量为17.06 GOPs。加解密网络的正确率达100%，破解网络正确率接近50%，硬件电路具备可配置和高安全特性。 |
| Abstract: | With the emergence of neural cryptography, an increasing number of studies employ neural networks to train encryption and decryption algorithms. While the use of adversarial networks enables end-to-end high-security encryption and decryption, challenges such as high overhead and low speed persist. To address this problem, this paper proposes a configurable encryption and decryption hardware design scheme for neural networks through the co-optimization of computational unit cores, data storage architectures, and data flow behavior. The proposed scheme first optimizes the encryption and decryption model for hardware compatibility, completing network training and quantization. Secondly, it employs a Winograd+DSP48-based convolution acceleration method, reducing the required multipliers from 96 to 32. Finally, a CPU control and scheduling system architecture is designed, integrating dynamic control of accelerator operation modes to achieve a high-performance configurable encryption and decryption hardware circuit. Experimental results demonstrate that the proposed solution achieves a maximum operating frequency of 133 MHz, with a power consumption of 32.4 mW, and a throughput of 17.06 GOPs. The accuracy rate of encryption and decryption in the network reaches 100%, the accuracy rate of cracking the network approaches 50%, and the hardware circuit features configurability and high security. |
| 参考文献 /References: | [1].Shukla N, Tiwari A. An empirical investigation of using ANN based N-state sequential machine and chaotic neural network in the field of cryptography[J]. Global journal of computer science and technology D: neural & artificial intelligence, 2012, 12(10):17-26. [2].Abadi M, Andersen D G. Learning to protect communications with adversarial neural cryptography [EB/OL]. [2025-03-21]. https://arxiv.org/abs/1610.06918. [3].COUTINHO M, DE OLIVEIRA ALBUQUERQUE R, BORGES F, et al. Learning perfectly secure cryptography to protect communications with adversarial neural cryptography[J]. Sensors, 2018, 18(5):1306. [4].LI Z Z, YANG X Y, SHEN K Q, et al. Information encryption communication system based on the adversarial networks foundation[J]. Neurocomputing, 2020, 415: 347-357. [5].KLEIN E, MISLOVATY R, KANTER I, et al. Synchronization of neural networks by mutual learning and its application to cryptography[EB/OL]. [2025-03-11]. https://papers.nips.cc/paper_files/paper/2004/file/5a45828dead8c065099cb653a2185df1-Paper.pdf. [6].SUN Y N, LO F P, LO B. Lightweight Internet of Things device authentication, encryption, and key distribution using end-to-end neural cryptosystems[J]. IEEE internet of things journal, 2022, 9(16):14978-14987. [7].SOLOVYEV R, KUSTOV A, TELPUKHOV D, et al. Fixed-point convolutional neural network for real-time video processing in FPGA[C]//2019 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus). Saint Petersburg and Moscow, Russia. IEEE, 2019:1605-1611. [8].JACOB B, KLIGYS S, CHEN B, et al. Quantization and training of neural networks for efficient integer-arithmetic- only inference[C]//2018 IEEE/CVF Conference on Computer Vision and Pattern Recognition. Salt Lake City, USA. IEEE, 2018:2704-2713. [9].CHEN X, LI J D, ZHAO Y. Hardware resource and computational density efficient CNN accelerator design based on FPGA[C]//2021 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA). Zhuhai, China. IEEE, 2021:204-205. [10].LI S Z, WANG Q, JIANG J F, et al. An efficient CNN accelerator using inter-frame data reuse of videos on FPGAs[J]. IEEE transactions on very large scale integration (VLSI) systems, 2022, 30(11):1587-1600. [11].KIM M, OH K, CHO Y, et al. A low-latency FPGA accelerator for YOLOv3-tiny with flexible layerwise mapping and dataflow[J]. IEEE transactions on circuits and systems I: regular papers, 2024, 71(3):1158-1171. |
| 备注/Memo: | 收稿日期：2025-07-16 宁波大学学报（理工版）网址：http://journallg.nbu.edu.cn/ 基金项目：国家自然科学基金（62474100，62134002）；浙江省“尖兵领雁+X”科技计划项目（2025C01063）；宁波市科创甬江2035重点研发计划（2024T016）；宁波大学“双一流”合作专项定向委托科技合作项目（HX2024000574，HX2025000106） 第一作者：涂江涛，硕士研究生，主要研究方向为集成电路和信息安全。E-mail: 2311100020@nbu.edu.cn *通信作者：张跃军，教授，主要研究方向为集成电路和信息安全。E-mail: zhangyuejun@nbu.edu.cn 宁波大学学报（理工版）网址：http://journallg.nbu.edu.cn/ |
