基于CNFET门电路设计
PDF下载 (314)唐伟童,汪鹏君*,郑雪松.基于CNFET门电路设计[J].宁波大学学报(理工版),2014,27(03):43-49.DOI:
TANG Wei-tong,WANG Peng-jun*,ZHENG Xue-song.Design of Low Power Ternary CNFET Gate Circuit[J].Journal of Ningbo University(Natural Science & Engineering Edition),2014,27(03):43-49.DOI:
| Title: | Design of Low Power Ternary CNFET Gate Circuit |
| 作者: | 唐伟童, 汪鹏君*, 郑雪松 |
| Author(s): | TANG Wei-tong, WANG Peng-jun*, ZHENG Xue-song |
| 关键词: | 低功耗; 碳纳米场效应晶体管; 多值逻辑; 门电路 |
| Keywords: | low power consumption; carbon nanotube field effect transistor; multi-valued logic; gate circuit |
| 分类号: | TP311.2 |
| 文献标识码: | A |
| 摘要: | 通过对碳纳米场效应晶体管(Carbon Nanotube Field Effect Transistor, CNFET)的研究, 提出一种基于CNFET的低功耗三值门电路设计方案. 该方案在分析CNFET结构及其不同尺寸的碳纳米管对应于不同阈值电压特性的基础上, 以多值逻辑理论为指导, 设计基于CNFET的三值反相器、与非门、或非门等单元门电路, 最后利用HSPICE对所设计的电路进行仿真. 结果表明: 所设计电路具有正确的逻辑功能, 与传统三值门电路相比, 三值CNFET门电路平均传输速度提高52.7%, 平均能耗节省54.9%. |
| Abstract: | By investigating the Carbon Nanotube Field Effect Transistor (CNFET), this paper proposes a design scheme of low power ternary CNFET gate circuit. The structure of CNFET and the various size of carbon nanotubes corresponding to the different threshold voltages are first analyzed, followed by designing ternary inverter, NAND gate, NOR gate and other unit gate circuit, all of which are implemented on the basis of multi-valued logic theory. Finally, HSPICE is used to simulate the circuit design. The results show that the designed circuits have expected logic functionality. Comparing with the traditional ternary gate circuit, the transmission speed of CNFET gate circuit increases on average by 52.7%, and energy is saved by 54.9% |
| 参考文献 /References: | [1].Vasundara P K S, Gurumurthy K S. Quaternary CMOS combinational logic circuits[C]. International Conference on Information and Multimedia Technology, 2009:538- 542. [2].汪鹏君, 梅凤娜. 三值绝热JKL触发器的设计[J]. 北京科技大学学报, 2012, 12(15):1464-1468. [3].吴训威. 多值逻辑电路设计原理[M]. 杭州: 杭州大学出版社, 1994:1-383. [4].Nepal K. Dynamic circuits for ternary computation in carbon nanotube based field effect transistors[C]. 8th IEEE International Conference on NEWCAS, 2010:53- 56. [5].王耀. 碳纳米管场效应管及其应用电路的建模分析[D]. 国防科学技术大学, 2008. [6].Deng Jie, Wong H S P. A Compact spice model for carbon-nanotube field-effect transistors including nonidealities and its application part I: Model of the intrinsic channel region[J]. IEEE Transactions on Electron Devices, 2012, 12(54):3186-3194. [7].Biswas S, Jameel K M, Haque R, et al. A novel design and simulation of a compact and ultra fast CNTFET multi-valued inverter using HSPICE[C]. 14th Interna- tional Conference on UK Sim, 2012:671-677. [8].Nan H, Ken C. Novel ternary logic design based on CNFET[C]. SOC Design Conference, 2010:115-118. [9].Vudadha C, Saiphaneendra P, Sreehari V, et al. CNFET based ternary magnitude comparator[C]. International Symposium on Communications and Information Tech- nologies (ISCIT), 2012:942-946. [10].Lin Sheng, Kim Y B, Lombardi F. A novel Cntfet-based ternary logic gate design[C]. IEEE International Midwest Symposium on Circuits and Systems Conference, 2009: 435-438. [11].Stanford Nanoelectronics Lab. Stanford CNFET model and Schottky barrier CNFET model[EB/OL]. [2013-07- 12]. http://nano.stanford.edu/model. php?id=23. [12].Bari S, Shonchoy N, Kabir F T, et al. Design and performance analysis of ultra fast CNFET comparator and CMOS implementation comparison[C]. 14th International Conference on UKSim, 2012:665-670. |
| 备注/Memo: | 收稿日期: 2013?09?18. 宁波大学学报(理工版)网址: http://journallg.nbu.edu.cn/ 基金项目: 国家自然科学基金(61234002); 浙江省自然科学基金(Z1111219). 第一作者: 唐伟童(1989-), 男, 四川平昌人, 在读硕士研究生, 主要研究方向: 逻辑电路. E-mail: twtw4747@163.com *通信作者: 汪鹏君(1966-), 男, 浙江奉化人, 博导/教授, 主要研究方向: 逻辑电路和低功耗集成电路. E-mail: wangpengjun@nbu.edu.cn 宁波大学学报(理工版)网址:http://journallg.nbu.edu.cn/ |